esc participates in two independent workpackages of the Iris programme.


ATM System Load Emulator

esc is a member of a team that defines the architecture and implements the Load Emulator of a future Air Traffic Management (ATM) System. The Load Emulator synthesizes interference in the forward and return radio link in different traffic loading scenarios. Together with a simulator of the telecommunication payload to be carried on the ATM satellite and the Satellite Channel Emulator of KU-band & L-band links, all the components will be integrated to a so called Verification Test Bench and used to evaluate and improve performance of the future ATM system.

Test Controller

Another task for esc is to develop Test Controller of the ATM Verification Test Bench (VTB). The Test Controller provides remote monitoring and control of all VTB elements from a centralized user position. There are 21 partners involved in the development of the VTB. Our delivery consists of an SW module, the host platform HW, documentation and integration of additional components like GUI or Result Processor provided by other subcontractors in the Iris/ANTARES project.

Iris Programme Overview

Iris, element 10 of the ESA’s ARTES (Advanced Research in Telecommunications Systems) programme, aims to develop    a new Air-Ground Communication system for Air Traffic Management (ATM). It is the satellite-based solution for the Single European Sky Air Traffic Management (ATM) Research (SESAR) programme. It supports the implementation of the Single European Sky by looking at all aspects of Air Traffic Management. It also intends to modernize communication infrastructure and increase safety for air traffic participants. By 2020 it will contribute to the modernization of air traffic management by providing digital data-links to cockpit crews in continental and oceanic airspace replacing a voice communication channel between the pilot and a controller.

IRIS/ANTARES (datasheet) IRIS_ANTARES_Datasheet